Volatile and nonvolatile memories are utilized more and more in mobile apparatuses such as MP3 players, personal multimedia players (PMP), mobile phones, notebook computers, personal digital assistants (PDA), etc. These mobile apparatuses require storage units with greater storage capacity for providing various functions (e.g., playing motion pictures). One example of larger capacity storage units is a multi-bit memory device in which each memory cell stores multi-bit data (e.g., 2 or more bits of data). For the sake of clarity, a memory cell storing multi-bit data is hereinafter referred to as multi-level cell (MLC).
When storing 1-bit data in a single memory cell, the memory cell is conditioned on a threshold voltage corresponding to one of two threshold voltage states. For example, at a given time the memory cell has one of two states representing data ‘1’ and data ‘0’. When a single memory cell stores 2-bit data, the memory cell is conditioned on a threshold voltage corresponding to one of four threshold voltage states. For example, the memory cell has one of four states representing data ‘11’, data ‘10’, data ‘00’, and data ‘01’. Namely, for n-bits per cell, 2n threshold voltage states are generally required.
In order to keep threshold voltage distribution profiles within corresponding windows, the threshold voltages may be adjusted to be dense within each window. For this adjustment, a programming method such as incremental step pulse programming (ISPP) may be used. In an example ISPP method, a threshold voltage shifts up by incremental rates of a program voltage upon repetition of programming loops. The distribution of threshold voltages may be controlled by lowering the incremental rate of the program voltage. FIG. 1 illustrates an example of an ISSP program cycle. Throughout the description herein, as a unit of programming operation, a ‘program loop’ refers to a period during which a word line is supplied with a program voltage Vpgm of a single pulse and a verify-read voltage Vfy corresponding to the program voltage. A ‘program cycle’ refers to a period during which memory cells are programmed using a plurality of program loops, according to an example ISPP method. Thus, a program cycle may include several program loops by which the program voltage Vpgm may increase. After each application of a program voltage, the programmed data is read using a verify-read voltage Vfy corresponding to the threshold voltage for a threshold voltage state. If the read data indicates programmed data, the program cycle ends. If not, the program voltage Vpgm is incremented and the next program loop takes place.
By using such an ISPP method, an MLC stores 2-bit data using LSB and MSB page programming. The most significant bit (MSB) refers to an upper bit of 2-bit data stored in the MLC and a least significant bit (LSB) refers to a lower bit of 2-bit data stored in the MLC. In a conventional NAND flash memory device using page unit programming, one page may be programmed by writing corresponding LSBs and MSBs in sequence.
FIG. 2 schematically shows a programming sequence for a conventional flash memory device including MLCs. Referring to FIG. 2, in programming an MLC, an LSB and an MSB may be programmed sequentially. In programming the LSB, the MLC selected for programming may be set to state ‘10’ from an erased state ‘11’, or may maintain the erased state ‘11’. Subsequently, in programming the MSB of the selected MLC, the MSB may transition to ‘0’. For example, the MLC may be programmed into a state ‘01’ from the erased state ‘11.’ Or an MLC, which has already been programmed into state ‘10’ in the LSB programming step, may maintain state ‘10’ or transition to state ‘00’. However, the LSB programming operation may involve a rising rate of cell threshold voltage relative to the MSB programming operation. In other words, the LSB programming operation may include a greater number of program loops than the MSB programming operation. As the number of program loops increases, coupling effects may be caused in adjacent memory cells.
FIG. 3A shows an LSB programming method for suppressing influence of rising threshold voltages due to coupling effects between adjacent cells and/or reducing coupling effects during LSB programming in an MLC flash memory device. Referring to FIG. 3A, during LSB programming, a selected MLC is programmed from erased state ‘11’ (10) into a provisional state ‘10*’ (20), but not into the state ‘10’ (30). In this example, a verifying read voltage Vfy2_low may be lower than a verifying read voltage Vfy2 corresponding to state ‘10’ (30). As a result, during LSB operation, coupling effects to adjacent cells may be reduced because a lower threshold voltage (e.g., lower verifying read voltage Vfy2_low) is used to transition the MLC from erased state ‘11’ to provisional state ‘10*’ (20).
FIG. 3B schematically shows a conventional MSB programming method performed subsequent to the LSB programming. Referring to FIG. 3B, Case1, Case2, and Case3 represent state transition patterns for transitioning an MSB from provisional state ‘10*’ or erased state ‘11’. An MLC may be programmed by transitioning an MSB from erased state ‘11’ (10) to state ‘01’ (40). An MLC, which has already been programmed into provisional state ‘10*’ (20), may be programmed to state ‘10’ (30) or state ‘00’ (50). In this example, even though the distribution profile of provisional state ‘10*’ (20) has been preliminarily extended by coupling effects of adjacent memory cells, the MSB programming operation may assist in making the distribution of threshold voltages result in a denser profile (‘10’ or ‘00’).
However, according to conventional data programming methods, programming times for MSBs may vary for Case1, Case2 and Case3. In programming one MSB page, Case1, Case2 and Case3 are performed sequentially in a number of program loops, and thus, programming time for one MSB page may be relatively long.